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Results from WP2 - Device Processing

Our goal is the optimization and qualification of GaN-on-Si power device processing on a 6-inch pilot line while targeting on-resistance < 20mΩ for 650V applications. Furthermore, we will develop devices for beyond 2000V applications by optimizing the substrate-removal technique for GaN-on-Si technology as well as achieving novel power devices based on bulk AlN.

From the lab:  

The partner Uni-Padova has demonstrated highly robust and reliable 650V D-mode power devices produced by the partner ONSemi. 

Normally-on GaN-on-silicon power devices produced by the partner OnSemi with negligible dynamic-Ron both at room temperature and high temperature up to 600V have been demonstrated by Uni-Padova. This has been possible by the optimization of the influence of carbon doping on 2DEG concentration that needs to be minimized through proper optimization of the C-doping level. Furthermore, the thickness of the unintentionally-doped GaN channel needs to be properly tuned. Also, leakage through the unintentionally-doped GaN layer must be optimized in order to favor charge-redistribution through the structure (which leads to a complete suppression of dynamic Ron) without reaching an excessive vertical leakage current. 



The partner CNRS showed lower current collapse in silicon-substrate-removal GaN devices observed subsequently to high bias switching operation
Best in class GaN-on-silicon power devices are currently limited by the buffer thickness in terms of breakdown voltage that cannot typically be grown above 6 to 7 µm, otherwise creating material defects or cracks due to the strain. This results in maximum lateral breakdown voltage below 2 kV. The partner CNRS has successfully developed a local silicon substrate removal technique to achieve state-of-the-art GaN-on-Si HEMTs with three-terminal lateral breakdown voltage of 3 kV. This achievement has been also obtained owing to the implementation of a thick high breakdown field AlN layer within the backside trenches followed by metal deposition to support the heat dissipation.
Finally, the partner CNRS also showed that current collapse characteristics of the substrate removed GaN-based MISHEMTs followed by thick PVD AlN and metal deposition were much lower as compared to reference devices (with silicon substrate).The double-pulsed ID-VG characteristics up to 550 V revealed significantly lower VTH shift and open channel current drop subsequent to high bias switching operation in the case of local silicon removal. These results indicate that in addition to the drastic blocking voltage enhancement, another key benefit provided by the local silicon removal approach is a lower current collapse owing to the removed interface between the AlN nucleation layer and the silicon substrate.